Joby Flight Research designs, develops, and flight-tests novel aircraft using a software-first autonomy approach. We build and deploy autonomy, perception, planning, and radar systems across conventional, electric, and hydrogen-electric aircraft in both CTOL and VTOL configurations.

We are looking for a hardware expert to bridge the analog and digital worlds. In this critical role, you will design cutting-edge, high-speed ADC and DAC sampling cards that interface with high-performance FPGAs via multi-gigabit JESD204B/C protocols. You will own the entire hardware lifecycle—from architecting wideband RF front-ends and ultra-low phase-noise clocking trees to guiding high-speed PCB layout, performing EM/SI simulations, and leading hands-on lab bring-up. If you thrive on solving complex signal integrity challenges and pushing the limits of mixed-signal data transport, we want to hear from you!

• Define mixed-signal architectures: Translate system-level requirements into hardware specifications for the RF front-end, data converters, and clocking trees.
• Component selection: Evaluate and select high-speed ADCs, DACs, ultra-low phase-noise clock generators/PLLs.
• JESD204 configuration: Define the JESD204B/C link parameters (lanes, frames, octets, subclass, and line rates) in collaboration with the FPGA team to ensure bandwidth and latency requirements are met.
• Design hardware: Create detailed schematics for the mixed-signal sampling cards, focusing on clean segregation of analog, digital, and power domains.
• Guide and perform layout: Route (or closely supervise the routing of) high-speed SerDes lanes, RF traces, and impedance-matched networks, preferably using Altium Designer.
• EM simulation: Use tools like HFSS, CST, or ADS to model and optimize RF transitions, balun layouts, and high-speed connector interfaces (e.g., FMC, FMC+, or custom backplanes).
• Initial board bring-up: Power on, test, and debug initial hardware prototypes in the lab.
• RF and Clock Characterization: Measure phase noise, jitter, insertion loss, and overall signal chain performance using VNAs, spectrum analyzers, and high-speed oscilloscopes.
• JESD link debugging: Troubleshoot high-speed serial link physical layers, including capturing eye diagrams and verifying SYSREF timing for deterministic latency.
• FPGA team integration: Work closely with FPGA/Firmware engineers to establish the JESD link, and debug link-layer data errors.
• Design documentation: Create comprehensive hardware design documents, test plans, and characterization reports for internal teams and manufacturing partners.

• Master degree or higher in Electrical Engineering or a related field.
• Familiar with RF/Microwave Engineering, Analog Circuit Design, Electromagnetic Theory, Digital Signal Processing, and High-Speed digital communications.
• System-level understanding of mixed-signal signal chains, from the RF front-end (impedance matching, baluns, anti-aliasing filters) through the high-speed data converters and into the FPGA.
• Deep knowledge of data converter fundamentals, including specifications like SNR, SFDR, ENOB, Nyquist zones, oversampling, and aliasing.
• Expertise in JESD204B/C protocols, including Subclass 1 deterministic latency, SYSREF alignment, framing, and link training troubleshooting.
• Precision clocking architectures, including designing for ultra-low jitter/phase-noise using PLLs, clock synthesizers, and careful clock distribution.
• Familiarity with FPGA multi-gigabit transceivers (SerDes), including equalization concepts (CTLE, DFE) and interacting with FPGA JESD IP cores.
• Familiar with FPGA programming: Xilinx Vivado and the design of components with VHDL.
• High-speed PCB design and layout, preferred with Altium Designer.
• Solid foundation in Signal Integrity (SI), specifically for routing multi-gigabit SerDes lanes (insertion/return loss, crosstalk).
• Good understanding of simulation and modelling tools (e.g., HFSS, CST, ADS) to model RF transitions, matching structures, and high-speed connector interfaces.
• System-level simulation capabilities, utilizing SPICE for analog circuits and IBIS models to simulate SerDes eye diagrams and ensure link closure.
• Good understanding of RF measurement, including hands-on experience with vector network analyzers (VNAs), spectrum analyzers, phase-noise analyzers, and high-performance oscilloscopes (for eye-diagram analysis).
• Practical hands-on experience in bringing up new mixed-signal hardware, soldering/modifying prototypes, and using both hardware probes and FPGA internal logic analyzers (e.g., SignalTap, ILA) to debug complex link failures.

This position must meet US export control compliance requirements, therefore a candidate must qualify as a “US Person” as defined by 22 C.F.R. § 120.15. “US Person” includes US Citizens, lawful permanent residents, refugees, or asylees.